;-------------------------------------------------
;Program: MOD-SYSTEM.ASM
;Date:    31 July 2002
; 
;By:      Dr. Marcus O. Durham, PhD, PE
;         Tulsa, OK, USA
;         mod@superb.org
;         www.ThewayCorp.com
;Copyright (c)2002.  All rights reserved
;

;*************************************************
;
;                     ANALOG TO DIGITAL
;
;*************************************************
;
;  SERIAL PERIPHERAL INTERFACE (SPI) is a common
;  protocol used for connection between a micro
;  processor and peripheral chips. It is used with
;  analog, memory, and sensor devices. The
;  controller is called the master while the 
;  peripheral is called the slave.
;
;  SPI protocol uses 4 basic lines.
;    MISO -master in, slave out is computer read
;    MOSI -master out, slave in is computer write
;    SCLK -serial clock is a software strobe or
;          pulse to shift data.
;    CS'  -chip select on low is a unique line
;          for each device.
;
;  The chip is selected by the CS' line. One
;  bit of data is placed on the data line. The bit
;  is shifted out on each clock strobe or pulse
;  transition.
;
;  The CS' line is made HI to stop or reset
;  an operation. The line is LO to select the chip
;  for transfer of info. The enable sequence is
;  unique, depending on the device.
;
;  The MISO / MOSI lines are HI or LO for each bit.
;
;  The SCLK line shifts data into the device
;  (MOSI) on a rising edge. So SCLK must be made 
;  LO then HI to input to the device from the 
;  controller.
;
;  The SCLK line shifts data out from the device
;  (MISO) on a falling edge. So SCLK must be made 
;  HI then LO to output from the device to the 
;  controller.
;
;
;-------------------------------------------------
ADCSPI:
;-------------------------------------------------
;
;  Analog to digital conversion (ADC) is shared on
;  SPI protocol. 
;
;  This device is National Semiconductor ADC12130.
;  It is a 12-bit plus sign result with 2 modes -
;  differential or single-ended.
;
;  The ADC requires the clock line be LO before
;  changing the enable (CS') status. So the ADC 
;  selection looks like this.
;    SELECT  - SCLK LO, CS' HI, CS'LO
;    DESELECT- SCLK LO, CS' HI
;
;  The falling edge on CS' always clocks out the
;  first data bit.
;
;  If only one peripheral is used, the CS' line
;  may be permanently low. In that case, there
;  is a slightly different operation. This mode
;  demands that the correct SCLK pulses be 
;  applied to keep synchronization. After the
;  power is supplied, the ADC expects to see 13
;  clock pulses for each1/0 sequence. This can
;  be modified with a command.
;
;  A command message must be written to the 
;  ADC to select the channel and the type of
;  signal, if other than default is desired.
;
;  A status register can be read to determine
;  the device operation. If the autocal command
;  is issued, the first read afterward is 
;  invalid because the registers are clear.
;  Therefore read status two times.
;
;  The ADC value is 12-bit plus sign. Therefore,
;  one byte is input, then 5-bits.
;
;  Clock rise & fall should not exceed 1usec.
;  The crystal is 11.059 MHz. This gives a time of
;  1.1 usec per instruction cycle. So no delay is
;  needed.
;
;  The CONV' line is pulled low to write any
;  commands. If it is high, only the output line
;  is active. 
;
;  The default on power up is 13-bit, MSB first,
;  10 CCLK acquisition time, user mode, no 
;  autocal, no autozero, and power up mode.
 
                              ;INITIAL
          LCALL  ADCEN        ;select ADC

                              ;COMMAND NOT USED
;         MOV    A,#0D0H      ;wr command 1101xxx
;         MOV    B,#8         ;8-bit loop
;         LCALL  SPIWR        ;write command

                              ;FIRST BIT AFTER CS
          CLR    A            ;clear shift reg
          MOV    C,SpMiso     ;first bit
          RLC    A

                              ;REST OF DATA IN
          MOV    B,#4         ;4-bit loop
          LCALL  SPIRD        ;input byte
          MOV    QikB         ;msb

          MOV    B,#8         ;8-bit loop
          LCALL  SPIRD        ;input byte
          MOV    QikA         ;lsb

          RET                 ;get outta here

;-------------------------------------------------
ADCEN:
;-------------------------------------------------
;
;  Enable the National Semiconductor ADC12130.
;
;  W/ crystal 11.059 MHz, 1.1 us/instruction cycle
;  Ret & calls are part of delay.

                              ;INITIAL
          CLR    SpClk        ;SPI clock

                              ;CHIP SELECT
          LCALL  LatCr        ;last value
          ANL    A,#11110110B ;clr to disable
          LCALL  MMIWR        ;write 
          ORL    A,#00000001B ;enable,falling edge
          LCALL  MMIWR        ;write 
          MOV    LatCr,A      ;keep value

          
          RET                 ;who is MR. Butler?

;-------------------------------------------------
SPIWR:
;-------------------------------------------------
;
;  Write a command on SPI lines. Data shift out on
;  rising edge.
;
SPWR1:    RLC    A            ;Rotate MSB to C
          CLR    SpClk        ;Clock pulse lo
          MOV    SpMosi,C     ;data to ship
          SETB   SpClk        ;CLK shift out bit
          DJNZ   B,SPWR1      ;not sent all bits
;
          RET                 ;Out of Dodge
;
;-------------------------------------------------
SPIRD:
;-------------------------------------------------
;
;  Read info on SPI lines. Shift in on trailing
;  edge of clock

          SETB   SpMiso       ;Make line an input

SPRD1:    SETB   SpClk        ;Clk high
          NOP                 ;assure < 1 usec 
          CLR    SpClk        ;Clock shift in bit
          MOV    C,SpMiso     ;data bit coming in
          RLC    A            ;Rotate bit to C
          DJNZ   B,SPRD1      ;Get all bits

          CLR    SpMiso       ;undo data as input

          RET                 ;Subroutine end

;*************************************************

          END                     ;Program end